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CPLD Design Division



Services Offered
bullet  Off The Shelf CPLD Designs
bullet  Design of CPLD's To A Given Specification
Below is depicted the test and evaluation rig used for the clock sub system.
Clock Device Test Rig




Example: A Current design : Altera CPLD, programmed as a clock sub system
This device enables you to build a clock using a handful of components and your own choice of display. The device has a 7 segment display driver built in. It can also be used to drive Nixie displays using just a few cheap transistors and resistors. Additionally, the device has a binary output, so it can be used as part of a larger timer or alarm system.
Shortform Data

     bullet  Single 32768Hz input reference source
     bullet  Switchable Between the 12 and 24Hr clock formats (single pin setting)
     bullet  The device can Drive 7 Segment Displays or Nixie Tubes (single pin setting)
     bullet  Binary output (always present)
     bullet  Simple clock setting arrangement
Applications
     bullet  Nixie Clock Design
     bullet  7 Segment Clock Design
     bullet  Time code source
     bullet  Digital timing and alarms

I can email a full data sheet for the device (in .PDF form) or it can be downloaded here : arrow
These device has been stored in an anti-static environment, both before and after programming.
The anti-static protection will be maintained during shipping. I can supply small production quantities of these.
Please email me for your requirements.
NOTE:
I can easily modify the contents, or compile the contents into another Altera type device.
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