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CPLD AND FPGA Design Division

Services Offered

Off The Shelf CPLD Designs

Design of CPLD's To A Given Specification


A Current design : Altera CPLD, programmed as a clock sub system

This device enables you to build a clock using a handful of components and your own choice of display. The device has a 7 segment display driver built in. It can also be used to drive Nixie displays using just a few cheap transistors and resistors. Additionally, the device has a binary output, so it can be used as part of a larger timer or alarm system.
Shortform Data
Single +5V Voltage Rail
Single 32768Hz input reference source
Switchable Between the 12 and 24Hr clock formats (single pin setting)
The device can Drive 7 Segment Displays or Nixie Tubes (single pin setting)
Binary output (always present)
Simple clock setting arrangement
Applications
Nixie Clock Design
7 Segment Clock Design
Time code source
Digital timing and alarms

I can email a full data sheet for the device (in .PDF form) or it can be downloaded here :

Clock Sub System Data
These device has been stored in an anti-static environment, both before and after programming.
The anti-static protection will be maintained during shipping. I can supply small production quantities of these.
Please email me for your requirements.

NOTE
I can easily modify the contents, or compile the contents into another Altera type device.
Below is depicted the test and evaluation rig used for the clock sub system.

Clock Device Test Rig







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